主题介绍
介绍了Ansys 进行Chip/Package/System协同仿真的方法,帮助设计者应对复杂IC设计中面临的PI/SI/ESD等挑战。
如有任何问题请点击以下链接进入答疑室与我们的技术专家进行交流互动
https://v.ansys.com.cn/live/e3f54d2a
演讲人简介
Sooyong Kim
该演讲为Ansys Simulation World 虚拟大会视频
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Hello everyone my name is Sooyong Kim from
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Ansys thanks
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for joining today's talk about simulation
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best practices for chip
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package system in IBP 2020 in this
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presentation we
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will
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share an overview of the key benefits of
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simulation and
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the capabilities required to realize the
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benefits
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through examples where we showcase how Ansys
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portfolio solutions are
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helping our customers design
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transformational products and close with
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the information on how
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to learn
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The evolution of chip design has been going
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on for
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40 years it's starting from 1980s in the
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beginning the
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designer was required to make the chip only
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to function
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hence only functional simulation where
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testing needed to be performed
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and designers were ok with it
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As the design requirement is more challenging
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and the technology
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advanced more than more domains of testing
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needed to be
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considered as chip design advanced to
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smaller and
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smaller following the Moore's law
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From functional verification and timing
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power and reliability due to
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the power
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And thermal impact due to the power
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And emission of electromagnetic waves makes
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the components to malfunction
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because of very small form factor of the
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design and
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very large power consumption of the
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components the complexity of
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the chip design now moving into so-called
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2.5 D or
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3D IC designs where now the customers are
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looking at
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much more challenges not only electrically
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and also it's a
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thermal and mechanical point of view as well
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To meet these requirements Ansys offers a
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development methodology CPS
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based on simulation
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This methodology is multiscale multi physical
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and multi user
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It is multi scale since it provides
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simulation functions that
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range from nanoscale ICs and other chip
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models to the
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scale of the matter servers unmanned aerial
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vehicles and so
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on
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Multiphysics capabilities enable the
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simulation of various physical phenomena in
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chip devices and systems including power
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integrity signal integrity and
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thermal integrity electrostatic discharge
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electromagnetic interference and electromagnetic
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compatibility heat
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transfer fluid dynamics and structure
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mechanics
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Finally the multi user aspect allows
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designers of chip package
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and systems to use a common platform to
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simulate together
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various physical phenomena in order to create
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more and more
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complex products for example the CPS design
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makes it easy
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to combine the ECAD and MCAD works that
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provides
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insight into the coupled interaction between
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the chip and the
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closer and the PCB through the interaction and
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exchange of
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models between team customers suppliers
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ecosystem coverage is important from analog
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company to digital company
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those analog and digital IP comany
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to SoC company
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and package company finally working
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with a tier one
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company through seamless modeling techniques
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to convey the design data
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from one company to the other for next level
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of
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simulation and verifications
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It is important to provide modeling
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technologies that can
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fit for various applications Ansys
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provides comprehensive list of
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modeling techniques for that
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There are significant challenges ahead of us
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to deliver next
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generation electronic system where power
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consumption reaches more than
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250 watt per system the data transfer rate
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requirement demands more
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than 112 Gbps data rate where
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2.5D
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or 3D IC design styles are considered to meet
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the
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performance requirement and due to the
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extreme form factors thermal
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reliability becomes essential than ever and
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at the same time
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electromagnetic sign up becomes more
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stringent
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While considering all these the designers
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can't afford to do
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fail to simulate a front all aspects of
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multiphysics with
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greater coverage since the cost of the
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failure is exponentially
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larger
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Based on the multiple customers feedback we
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believe CPS simulation
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benefits the designers by giving 10X
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improvement in simulation time
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has resulted in 66% design cycle time
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reduction
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and gave at least 30%
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reduction in cost in production
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We would like to touch upon the simulation
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capabilities of
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CPS solution for
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the various domains of simulation areas that
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we are actively
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used in the field for power integrity
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signal integrity
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ESD EMI EMC thermal mechanical integrity
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From an integrated point of view the designers
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has
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challenges of creating design that can
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minimize the power consumption first with the
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power Ansys
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provides solutions to reduce the power and
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monitor power
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consumption during all the RTL design
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cycles the designers then
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would like to verify if there the power
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delivery network
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is robust and satisfy the margin requirements
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that would make
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the design function properly
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The designers need to minimize the noise by
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decoupling properly
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and minimize the current flow on the routing
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that satisfies
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the electromigration requirements of the chip
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or design to make sure the design can sustain
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functioning
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properly for many many years
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Ansys provides a power delivery network
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signoff all
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the way from transistor to system
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Ansys does that by providing proper CPS model
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techniques from chip
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aware system power integrity to system
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aware chip power
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integrity customers utilized various reports
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from Ansys power integrity platform
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steady or transient simulation and current
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voltage signature from the
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simulations along with impedance profile the
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customer
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will be able to figure out best decoupling
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schemes considering
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power plane resonance of the entire system
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all the way
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from chip to board and the systems
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From a signal integrity point of view
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the data exchange rate ever increases with HVM
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memory types
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as interposed design advances in
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2.5 D design styles
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The recent PCIE
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5.0 technology is the next evolution
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that will set the standard for speed of its
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32 giga
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transfer per second bandwidth
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Ansys provides industry leading solvers
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to meet the requirement
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with
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3D full wave and hybrid EM solvers available
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to the
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customers
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We also support various IBIS and IBIS AMI in
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modeling generation
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and their simulations our signature chip
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signal model technique
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Comprises of chip level power noise modeling
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and power noise
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what if impact for power
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noise aware SSO
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analysis for HVM like designs
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The virtual compliance kit tool gives very
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simple reporting structures
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where the design does not need to define any
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parameters
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to find the failure of SI requirement instead
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Ansys virtual
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compliance kit will give nicely created
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signoff report with
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a simple pass fail marks in a nice HTML
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format
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Recent advancement on the handling more of
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the silicon data
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for SI analysis point of view in Ansys
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portfolio gives
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more confidence to the customers in silicon
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integration area
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silicon integrity area
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For EMI EMC analysis side channel attack
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analysis
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becomes
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an important topic recently there was no
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tools that can
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simulate properly all the possible key
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scenarios on the security
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attack
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Ansys is unique because Ansys is the only
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solution out
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there to come up with all possible scenarios
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quickly and
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accurately for side channel attack in
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every front multiphysics domain
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Ansys provide all the detection of the EMI EMC
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issues by
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creating and applying the proper modeling of
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any EM sources
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to system level analysis helping the
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designers identify
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critical areas acceptable to the failure EM
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risk is now
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bigger than ever within silicon designs
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itself as well because
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of the heterogeneous integration within SoC
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designs and heterogeneous integration
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including antenna design closer together
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within
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2.5 D and 3D
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IC structures
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Ansys provides accurate solvers from chip
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level to system
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level to identify and fix the critical areas
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for EM
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ESD noise needs to be minimized properly
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by many
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different circuits in chip level and system
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levels those ESD
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devices need to be validated in various
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situations starting from
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touching the circuit by hand accidentally
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to manufacturing process where ESD event
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occurs inevitably
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The designers can confirm
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ESD event inside the chip design by
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mimicking ESD
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discharging event through simulation in all
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details at the wire
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level with Ansys solution
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Ansys can provide our chip level ESD
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modeling techniques of
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compact ESD chip model to confirm ESD noise
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at the
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system level with the chip level modeling
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technique as well
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The designers were
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properly able to identify and fix the
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critical areas of
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ESD event using our simulation techniques
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for the entire systems
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00:13:33.31 - 00:13:36.11 28
from transistor to the board
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00:13:44.97 - 00:13:48.85 44
Thermal mechanical issue cannot be separated
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00:13:48.85 - 00:13:49.20 4
from
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00:13:49.20 - 00:13:53.86 42
electrical integrity and the very accurate
-
00:13:53.86 - 00:13:56.75 33
electrical integrated solution in
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00:13:56.86 - 00:14:01.52 44
conjunction with thermal mechanical analysis
-
00:14:01.52 - 00:14:03.49 19
is the complete way
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00:14:03.49 - 00:14:08.22 39
3D IC design style and complex material
-
00:14:08.22 - 00:14:09.80 20
structures in system
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00:14:09.91 - 00:14:14.64 36
makes more need for complete thermal
-
00:14:14.64 - 00:14:16.75 28
mechanical analysis of ahead
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00:14:16.85 - 00:14:19.70 27
of time in the design cycle
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00:14:19.70 - 00:14:25.21 41
Early prototyping in system planning with
-
00:14:25.21 - 00:14:28.77 33
electrothermal mechanical becomes
-
00:14:28.77 - 00:14:32.73 38
a key area and Ansys is ready for that
-
00:14:35.01 - 00:14:39.09 40
Our solution advances all the way to the
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00:14:39.09 - 00:14:40.27 17
FinFET transistor
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00:14:40.36 - 00:14:44.44 43
pins to entire system with highest capacity
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00:14:44.44 - 00:14:45.71 15
of dealing with
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00:14:45.80 - 00:14:49.88 42
heterogeneous materials that were recently
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00:14:49.88 - 00:14:50.61 10
introduced
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00:14:50.61 - 00:14:54.92 43
Even with very limited information provided
-
00:14:54.92 - 00:14:57.03 24
for the complete thermal
-
00:14:57.12 - 00:15:01.44 45
mechanical modeling for each components Ansys
-
00:15:01.44 - 00:15:03.74 23
provides a flexible way
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00:15:03.84 - 00:15:08.15 44
of creating such prototyping model and apply
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00:15:08.15 - 00:15:10.74 27
for reliable electrothermal
-
00:15:10.74 - 00:15:12.50 19
mechanical analysis
-
00:15:21.35 - 00:15:25.25 39
Ansys provides proven solutions for the
-
00:15:25.25 - 00:15:27.77 35
electronic system design addressing
-
00:15:27.86 - 00:15:31.76 44
new challenges in 5G network infrastructures
-
00:15:31.76 - 00:15:33.84 24
and helping cutting down
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00:15:33.93 - 00:15:37.84 45
turn around time and resources by at least or
-
00:15:37.84 - 00:15:38.27 4
half
-
00:15:38.27 - 00:15:42.40 40
to advanced simulations engines and goes
-
00:15:42.40 - 00:15:44.51 27
beyond Moore's law tackling
-
00:15:44.61 - 00:15:48.74 45
multiphysics and multiscale changes in new 3D
-
00:15:48.74 - 00:15:50.21 15
IC design trend
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00:15:50.21 - 00:15:54.09 43
The real customer case studies can be found
-
00:15:54.09 - 00:15:54.52 6
in the
-
00:15:54.61 - 00:15:55.56 11
links below
-
00:15:55.56 - 00:15:58.86 42
And in order to contact us there is a link
-
00:15:58.93 - 00:16:01.61 34
also as well for you to contact us
-
00:16:09.27 - 00:16:13.18 28
There are abundant resources
-
00:16:13.18 - 00:16:14.57 22
available for you from
-
00:16:14.57 - 00:16:19.49 39
white papers application notes customer
-
00:16:19.49 - 00:16:21.46 23
stories tips and tricks
-
00:16:21.46 - 00:16:26.36 30
Webinars to Ansys Learning Hub
-
00:16:26.36 - 00:16:29.56 36
Go check out the locations available
-
00:16:29.56 - 00:16:30.89 16
to find out more
-
00:16:37.45 - 00:16:41.93 43
You will be able to find the break sessions
-
00:16:41.93 - 00:16:42.13 3
for
-
00:16:42.23 - 00:16:45.63 34
each multiphysics area in this IBP
-
00:16:45.63 - 00:16:50.64 39
video for more details for the customer
-
00:16:50.64 - 00:16:51.76 15
example and the
-
00:16:51.87 - 00:16:56.88 42
result please check out the full IBP video
-
00:16:56.88 - 00:16:57.44 7
and PDF
-
00:16:57.55 - 00:17:00.23 24
available in the session
-
00:17:07.97 - 00:17:13.07 43
In order to learn more about Ansys products
-
00:17:13.07 - 00:17:13.75 5
go to
-
00:17:13.86 - 00:17:14.32 4
www.
-
00:17:14.32 - 00:17:15.22 6
ansys.
-
00:17:15.22 - 00:17:20.32 40
com/products you will find more products
-
00:17:20.32 - 00:17:22.82 27
listed for its capabilities
-
00:17:22.93 - 00:17:24.75 16
and applications
-
00:17:24.75 - 00:17:28.58 44
The table shows overall product lines we can
-
00:17:28.58 - 00:17:29.27 8
use this
-
00:17:29.35 - 00:17:31.83 26
table to guide you through
-
00:17:31.83 - 00:17:36.28 41
what are the available product lines from
-
00:17:36.28 - 00:17:37.27 4
RANS
-
00:17:37.37 - 00:17:41.33 38
right up to SI wave HFSS Q3D or Icepak
-
00:17:41.43 - 00:17:45.39 41
Ansys Electronic Enterprise product lines
-
00:17:54.52 - 00:17:58.03 44
Thanks for joining CPS session of simulation
-
00:17:58.03 - 00:17:59.36 17
best practices in
-
00:17:59.44 - 00:18:02.96 39
IBP 2020 we look forward to meeting and
-
00:18:02.96 - 00:18:03.66 14
supporting you
-
00:18:03.74 - 00:18:07.26 40
in the future in the journey of creating
-
00:18:07.26 - 00:18:08.28 16
ever challenging
-
00:18:08.28 - 00:18:09.68 18
electronic systems