Hello everyone my name is Sooyong Kim from

Ansys thanks

for joining today's talk about simulation

best practices for chip

package system in IBP 2020 in this

presentation we

will

share an overview of the key benefits of

simulation and

the capabilities required to realize the

benefits

through examples where we showcase how Ansys

portfolio solutions are

helping our customers design

transformational products and close with

the information on how

to learn

The evolution of chip design has been going

on for

40 years it's starting from 1980s in the

beginning the

designer was required to make the chip only

to function

hence only functional simulation where

testing needed to be performed

and designers were ok with it

As the design requirement is more challenging

and the technology

advanced more than more domains of testing

needed to be

considered as chip design advanced to

smaller and

smaller following the Moore's law

From functional verification and timing

power and reliability due to

the power

And thermal impact due to the power

And emission of electromagnetic waves makes

the components to malfunction

because of very small form factor of the

design and

very large power consumption of the

components the complexity of

the chip design now moving into so-called

2.5 D or

3D IC designs where now the customers are

looking at

much more challenges not only electrically

and also it's a

thermal and mechanical point of view as well

To meet these requirements Ansys offers a

development methodology CPS

based on simulation

This methodology is multiscale multi physical

and multi user

It is multi scale since it provides

simulation functions that

range from nanoscale ICs and other chip

models to the

scale of the matter servers unmanned aerial

vehicles and so

on

Multiphysics capabilities enable the

simulation of various physical phenomena in

chip devices and systems including power

integrity signal integrity and

thermal integrity electrostatic discharge

electromagnetic interference and electromagnetic

compatibility heat

transfer fluid dynamics and structure

mechanics

Finally the multi user aspect allows

designers of chip package

and systems to use a common platform to

simulate together

various physical phenomena in order to create

more and more

complex products for example the CPS design

makes it easy

to combine the ECAD and MCAD works that

provides

insight into the coupled interaction between

the chip and the

closer and the PCB through the interaction and

exchange of

models between team customers suppliers

ecosystem coverage is important from analog

company to digital company

those analog and digital IP comany

to SoC company

and package company finally working

with a tier one

company through seamless modeling techniques

to convey the design data

from one company to the other for next level

of

simulation and verifications

It is important to provide modeling

technologies that can

fit for various applications Ansys

provides comprehensive list of

modeling techniques for that

There are significant challenges ahead of us

to deliver next

generation electronic system where power

consumption reaches more than

250 watt per system the data transfer rate

requirement demands more

than 112 Gbps data rate where

2.5D

or 3D IC design styles are considered to meet

the

performance requirement and due to the

extreme form factors thermal

reliability becomes essential than ever and

at the same time

electromagnetic sign up becomes more

stringent

While considering all these the designers

can't afford to do

fail to simulate a front all aspects of

multiphysics with

greater coverage since the cost of the

failure is exponentially

larger

Based on the multiple customers feedback we

believe CPS simulation

benefits the designers by giving 10X

improvement in simulation time

has resulted in 66% design cycle time

reduction

and gave at least 30%

reduction in cost in production

We would like to touch upon the simulation

capabilities of

CPS solution for

the various domains of simulation areas that

we are actively

used in the field for power integrity

signal integrity

ESD EMI EMC thermal mechanical integrity

From an integrated point of view the designers

has

challenges of creating design that can

minimize the power consumption first with the

power Ansys

provides solutions to reduce the power and

monitor power

consumption during all the RTL design

cycles the designers then

would like to verify if there the power

delivery network

is robust and satisfy the margin requirements

that would make

the design function properly

The designers need to minimize the noise by

decoupling properly

and minimize the current flow on the routing

that satisfies

the electromigration requirements of the chip

or design to make sure the design can sustain

functioning

properly for many many years

Ansys provides a power delivery network

signoff all

the way from transistor to system

Ansys does that by providing proper CPS model

techniques from chip

aware system power integrity to system

aware chip power

integrity customers utilized various reports

from Ansys power integrity platform

steady or transient simulation and current

voltage signature from the

simulations along with impedance profile the

customer

will be able to figure out best decoupling

schemes considering

power plane resonance of the entire system

all the way

from chip to board and the systems

From a signal integrity point of view

the data exchange rate ever increases with HVM

memory types

as interposed design advances in

2.5 D design styles

The recent PCIE

5.0 technology is the next evolution

that will set the standard for speed of its

32 giga

transfer per second bandwidth

Ansys provides industry leading solvers

to meet the requirement

with

3D full wave and hybrid EM solvers available

to the

customers

We also support various IBIS and IBIS AMI in

modeling generation

and their simulations our signature chip

signal model technique

Comprises of chip level power noise modeling

and power noise

what if impact for power

noise aware SSO

analysis for HVM like designs

The virtual compliance kit tool gives very

simple reporting structures

where the design does not need to define any

parameters

to find the failure of SI requirement instead

Ansys virtual

compliance kit will give nicely created

signoff report with

a simple pass fail marks in a nice HTML

format

Recent advancement on the handling more of

the silicon data

for SI analysis point of view in Ansys

portfolio gives

more confidence to the customers in silicon

integration area

silicon integrity area

For EMI EMC analysis side channel attack

analysis

becomes

an important topic recently there was no

tools that can

simulate properly all the possible key

scenarios on the security

attack

Ansys is unique because Ansys is the only

solution out

there to come up with all possible scenarios

quickly and

accurately for side channel attack in

every front multiphysics domain

Ansys provide all the detection of the EMI EMC

issues by

creating and applying the proper modeling of

any EM sources

to system level analysis helping the

designers identify

critical areas acceptable to the failure EM

risk is now

bigger than ever within silicon designs

itself as well because

of the heterogeneous integration within SoC

designs and heterogeneous integration

including antenna design closer together

within

2.5 D and 3D

IC structures

Ansys provides accurate solvers from chip

level to system

level to identify and fix the critical areas

for EM

ESD noise needs to be minimized properly

by many

different circuits in chip level and system

levels those ESD

devices need to be validated in various

situations starting from

touching the circuit by hand accidentally

to manufacturing process where ESD event

occurs inevitably

The designers can confirm

ESD event inside the chip design by

mimicking ESD

discharging event through simulation in all

details at the wire

level with Ansys solution

Ansys can provide our chip level ESD

modeling techniques of

compact ESD chip model to confirm ESD noise

at the

system level with the chip level modeling

technique as well

The designers were

properly able to identify and fix the

critical areas of

ESD event using our simulation techniques

for the entire systems

from transistor to the board

Thermal mechanical issue cannot be separated

from

electrical integrity and the very accurate

electrical integrated solution in

conjunction with thermal mechanical analysis

is the complete way

3D IC design style and complex material

structures in system

makes more need for complete thermal

mechanical analysis of ahead

of time in the design cycle

Early prototyping in system planning with

electrothermal mechanical becomes

a key area and Ansys is ready for that

Our solution advances all the way to the

FinFET transistor

pins to entire system with highest capacity

of dealing with

heterogeneous materials that were recently

introduced

Even with very limited information provided

for the complete thermal

mechanical modeling for each components Ansys

provides a flexible way

of creating such prototyping model and apply

for reliable electrothermal

mechanical analysis

Ansys provides proven solutions for the

electronic system design addressing

new challenges in 5G network infrastructures

and helping cutting down

turn around time and resources by at least or

half

to advanced simulations engines and goes

beyond Moore's law tackling

multiphysics and multiscale changes in new 3D

IC design trend

The real customer case studies can be found

in the

links below

And in order to contact us there is a link

also as well for you to contact us

There are abundant resources

available for you from

white papers application notes customer

stories tips and tricks

Webinars to Ansys Learning Hub

Go check out the locations available

to find out more

You will be able to find the break sessions

for

each multiphysics area in this IBP

video for more details for the customer

example and the

result please check out the full IBP video

and PDF

available in the session

In order to learn more about Ansys products

go to

www.

ansys.

com/products you will find more products

listed for its capabilities

and applications

The table shows overall product lines we can

use this

table to guide you through

what are the available product lines from

RANS

right up to SI wave HFSS Q3D or Icepak

Ansys Electronic Enterprise product lines

Thanks for joining CPS session of simulation

best practices in

IBP 2020 we look forward to meeting and

supporting you

in the future in the journey of creating

ever challenging

electronic systems