Challenges and solutions of PI sign-off for next generation large scale chips with TSMC 7nm

主题介绍

With the evolution of process technology, design margin keeps decreasing. Process variation becomes non-Gaussian at lower voltage. Accuracy of power calculation and reliability check become more and more important. In addition, as the scale and complexity of chips increase, legacy multi-threads solution cannot meet PI(power integrity) simulation requirements, and vector-based PI simulation becomes more and more difficult.

The key approaches in our solution are as follows:

  • Selection of Vector Scenario

PowerArtist's profile-power feature enables fast scanning of RTL waveforms at millisecond-level. This feature can help to obtain the worst DPDT (Delta Power/Delta Time) cycle and the worst power cycle. After cycle-selection, these RTL waveforms will be converted to gate-level with name-mapping and propagation(no post-simulation needed).

  • Coverage of Process Corner

The highly parallel elastic computing capabilities of RedHawk-SC helped us to cover multiple processes, such as SSGNP, FFGNP and LT, especially at advanced technology node.

  • Accuracy of power calculation

Based on design’s physical parameters and TSMC’s device model, power conversion ratio of each PVT corner is computed by hspice simulation.

  • Analysis of thermal-aware statistic EM

With narrow 3-D fin structure and lower thermal conductivity in substrate, local temperature on FinFET device can be higher than planar MOS device, which will degrade lifetime of interconnections significantly. 

如有任何问题请点击以下链接进入答疑室与我们的技术专家进行交流互动:

芯片半导体答疑室 https://v.ansys.com.cn/live/ec7a78b2

演讲人简介

Junjie Chen , Sr. Physical Design Engineer 

Joined ZTE‘s back-end deisgn department in 2016,working on PI analysis of advanced TSMC technologe.

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